This invention generally relates to electronic systems and in particular it relates sense amplifiers that are capable of sensing small differential voltages between two inputs with full voltage range.
The typical prior art sense amplifier is capable of detecting a small differential voltage between two inputs close to the source voltage (VDD). It is widely used in memory with bitlines pre-charged to voltage VDD. However, this type of sense amplifier cannot sense the differential voltage between two inputs that are both below Vtn (the threshold voltage of an NMOS transistor).
One prior art sense amplifier that is capable of sensing a small differential voltage between two inputs REF and DATA close to 0V is shown in FIG. 1. This circuit has output signals OUT and OUT#, clock signal CLK, and enable signal EN. This prior art between two inputs that are both above voltage VDD minus Vtp (the threshold voltage of a PMOS transistor).
FIG. 2 illustrates another prior art sense amplifier that has a wide input range. However, it does not work in low power supply application (sub 1V). After equalization, the voltage at node N10 and the voltage at node N20 are at an intermediate level between the power supply voltage level VDD and ground level. This circuit can not sense differential voltages between nodes REF and DATA if (VN10/VN20xe2x88x92Vtp) less than VREF/VDATA less than Vtn, where VN10 is the voltage at node N10, VN20 is the voltage at node N20, VREF is the voltage at node REF, and VDATA is the voltage at node DATA. The outputs of this circuit are nodes OUTPUT and OUTPUT#. An enable signal is applied at node EN.
FIG. 3 illustrates a prior art differential voltage sense circuit to detect the state of a CMOS process compatible fuse RFUSE. It also cannot sense the differential voltages between two input signals that are both below Vtn.
A sense amplifier that is capable of sensing small differential voltage between two inputs with full voltage range includes a first inverter; a second inverter cross coupled with first inverter; a first transmission gate coupled between a reference node and an input of the first inverter; a second transmission gate coupled between a data node and an input of the second inverter; a pull-up enable switch coupled between a high side voltage source node, and the first and second inverters; and a pull-down enable switch coupled between a low side voltage source node, and the first and second inverters.